Author: Potter White
Date: August 2025

Project Overview

Situation: In a custom project based on the Rockchip RK3568 SoC, the objective was to enable the LVDS, MIPI-DSI, and HDMI 2.0 display interfaces, either simultaneously or independently. The LVDS interface was required to output a 1920x1080@30Hz video stream to an FPGA, exceeding the SoC’s official datasheet specifications (max 1280x800). The HDMI and MIPI interfaces needed to bypass EDID detection and force a fixed 1080p@60Hz output. These data paths were unconfigured in the initial BSP, requiring a complete bring-up from scratch.

My Role & Contributions: As the project’s BSP engineer, I was solely responsible for the entire display subsystem bring-up and integration task. My core contribution was performing all configuration and debugging purely at the software level, driven by in-depth analysis of datasheets and kernel source code:

Conducted a deep-dive analysis and mapped the complete data flow of the RK3568 display subsystem, from Memory -> VOP -> Interface Controllers -> Combo PHY.
Led and executed the precise configuration of the Device Tree (DTS), correctly setting up VOP routing, timing parameters, and PHY multiplexing for all three interfaces (LVDS, MIPI-DSI, HDMI).
Successfully drove the SoC’s physical layer (PHY) to output correct digital video signals through meticulous DTS configuration, laying a solid foundation for subsequent signal handshaking with the FPGA and initialization of HDMI displays.
Achieved stable video output exceeding official specifications, successfully delivering a 1920x1080@30Hz signal via the LVDS interface within the SoC’s clock frequency limits, which was successfully received and locked by the FPGA.
Distilled the entire debugging process into a Standard Operating Procedure (SOP) and technical documentation, providing a clear and efficient framework for all future display interface bring-up tasks for the team.

My Methodology: Display Interface Debugging SOP

To systematically address complex “display bring-up” or “signal integration” challenges, I developed a four-phase SOP. This process breaks down the ambiguous debugging task into clear, verifiable steps, enabling rapid problem isolation between the SoC’s software configuration and the peer device (FPGA/display panel).

How-to: Display Interface Debugging Standard Operating Procedure (SOP): Details the four critical phases, from information gathering to low-level validation.
How-to: Forcing HDMI Configuration on RK3568: Documents the process of forcing HDMI connection status and resolution via driver modification and DTS.
Analysis of Key Concepts in the Rockchip Display Subsystem: Summarizes core concepts like VOP and DRM port routing.
LVDS Bring-Up on RK3568: A Data Flow Study: Provides an in-depth analysis of the complete LVDS data path from memory to the physical pins.

Results & Verification

Following the SOP, I successfully enabled all target display interfaces on the RK3568. All configurations were verified through software utilities and feedback from the peer devices.

Kernel Mode Validation (modetest)

The modetest utility confirmed that the kernel successfully created and applied the forced modes for each interface, bypassing EDID detection. Below are examples for each interface:

Connectors:
id      encoder status          name            size (mm)       modes   encoders
172     171     connected       LVDS-1          0x0             1       171
  modes:
        index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
  #0 1920x1080 29.41 1920 1968 2000 2040 1080 1083 1088 1111 66660 flags: nhsync, nvsync; type: preferred, driver
  ...

174     173     connected       HDMI-A-1        0x0             1       173
  modes:
        index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
  #0 1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: phsync, pvsync; type: preferred
  ...

190     189     connected       DSI-1           68x121          1       189
  modes:
        index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
  #0 1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: nhsync, nvsync; type: preferred, driver
  ...

Conclusion: The kernel’s DRM framework operated as expected according to the DTS configuration, with correct clock-frequency and timing parameters loaded for all interfaces.

Final Outcomes

Successful Bring-up of Multiple Interfaces: The LVDS, MIPI-DSI, and HDMI 2.0 interfaces were all capable of outputting video streams at their specified resolutions on demand.
Successful FPGA Integration: The FPGA development team confirmed stable reception of the 1920x1080@30Hz LVDS video stream from the RK3568, with no frame drops or screen corruption.
Exceeded Datasheet Specifications: This work validated that the RK3568’s LVDS interface is capable of outputting resolutions higher than officially specified, providing valuable data for future product designs, provided that clock constraints are met.

Tech Stack & Tools

Hardware Platform: Rockchip RK3568 SoC, FPGA (as the receiver for all three interfaces)
Software Environment: Linux Kernel 5.10, U-Boot, Device Tree
Core Technologies: Embedded Linux BSP, DRM (Direct Rendering Manager), VOP2, LVDS/MIPI D-PHY Combo, HDMI 2.0, Device Tree (DTS)
Debugging Tools:
- Hardware: Serial Console
- Software: dmesg, sysfs, modetest, Kernel source code review and analysis

RK3568 Platform: Display Subsystem Bring-up and Multi-Interface Debugging